Research Article | Open Access | Download PDF
Volume 2 | Issue 5 | Year 2012 | Article Id. IJPTT-V2I5N1P5 | DOI : https://doi.org/10.14445/22492615/IJPTT-V2I5N1P5Network Data Security Using FPGA
Ms.P. Thamarai, Mr.B. karthik
Citation :
Ms.P. Thamarai, Mr.B. karthik, "Network Data Security Using FPGA," International Journal of P2P Network Trends and Technology (IJPTT), vol. 2, no. 5, pp. 24-27, 2012. Crossref, https://doi.org/10.14445/22492615/IJPTT-V2I5N1P5
Abstract
This paper approaches a new and simple technique
to develop the RSA algorithm using FPGA that can be used as a standard device
in the secured communication system. This RSA algorithm is implemented in the
FPGA with the help of VHDL. A simple nested loop addition and subtraction have
been used in order to implement the RSA operation. This results in very low
frequency requirement to perform this operation with consideration of high
speed by reducing the gate counts with low power consumption of whole circuit,
multiple key size support and low cost compared to earlier methods. The
information to RSA encryption side is in the form of statement and the same
will appear in the decryption side and its real time input/output also achieved
effectively. The hardware design is targeted on Xilinx Spartan 3E device and it
supports lower versions as well. The RSA algorithm design has made use of 951
total equivalent gate counts and achieved a clock frequency of 35.00MHz.
Keywords
Cryptography, FPGA, VHDL, Security, Communication.
References
[1] M.K. Hani, T.S. Lin, N. Shaikh-Husin, “FPGA Implementation of RSA Public-Key Cryptographic Coprocessor”, Proceedings of TENCON, vol. 3, pp. 6- 11, Kuala Lumpur, Malaysia, 2000.
[2] Y.S. Kim, W.S. Kang, J.R. Choi, “Implementation of 1024-bit Modular Processor for RSA Cryptosystem”, Proceedings of Asia-Pasific Conference on ASIC, pp. 187-190, Cheju Island, Korea, 2000.
[3] M. Shand and J. Vuillemin, “Fast Implementation of RSA Cryptography”, Proceedings of 11th IEEE Symposium on Computer Arithmetic, pp. 252-259, Windsor, Ontario,1993.
[4] C. Brueggen, J. Singh, D. Lord, B. Siever, D. Sullins, “A Hardware Approach to RSA Encryption”, Department of Electrical and Computer Engineering University of Missouri-Rolla, pp. 1-14, Citing Internet Sources; URL: http://www.mentor.com/partners/hep/HDLcontest.htm.
[5] Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman and Sazzad Hussain “FPGA Implementation of RSA Encryption Engine with Flexible Key Size” Proceedings of International Journal of Communications, Issue 3, volume 1, 2007.
[6] Rivest, R., Shamir, A., and Adleman, L, “A Method for Obtaining Digital Signatures and Public Key Cryptosystems”, Communications of the ACM, 1978, vol.21, no. 2, pp. 120-126.
[7] C. K. Koc., “RSA Hardware Implementation. Technical Report TR 801”, RSA Laboratories, 1996, pp. 1-24.
[8] Thomas Wollinger, Jorge Guajardo, Christof Paar “Cryptography on FPGAs: State of the Art Implementations and Attacks” Proceedings of ACM Special Issue Security and Embedded Systems Vol. No. March 2003.
[9] John Fry, Martin Langhammer, “RSA & Public Key Cryptography in FPGAs”,Proceedings of ALTERA Corporation Journal.
[10] Xilinx Manual,“Data Encryption using DES/Triple-DES Functionality in Spartan-II FPGAs” released on 03/09/2000.