International Journal of P2P
Network Trends and Technology

Research Article | Open Access | Download PDF
Volume 3 | Issue 3 | Year 2013 | Article Id. IJPTT-V3I4P2 | DOI : https://doi.org/10.14445/22492615/IJPTT-V3I4P2

Low Power High Speed Two’s Complement Multiplier

P. Arulbalaji, Mrs. K. Vanitha

Citation :

P. Arulbalaji, Mrs. K. Vanitha, "Low Power High Speed Two’s Complement Multiplier," International Journal of P2P Network Trends and Technology (IJPTT), vol. 3, no. 3, pp. 8-12, 2013. Crossref, https://doi.org/10.14445/22492615/IJPTT-V3I4P2

Abstract

To reduce the area of partial product array size and improve the speed which is generated by a radix-4 Modified Booth Encoded Multiplier is used. This reduction is possible without any increase in the delay of the partial product generation stage. This reduction provides faster compression of the partial product array and regular layouts in two’s complement multiplier. The proposed method is that the Radix-4 (Fixed-Width) Modified Booth Multipliers are used to achieve the low power and increase the speed by modifying the partial product matrix size. The Multiplier design implemented using Xilinx. The results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay. It is compared with Radix-4 (short bit-width) Modified booth encoded Multiplier.

Keywords

Multiplication, Modified Booth Encoding, partial product array, Fixed-width Modified Booth multiplier.

References

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